TSMC Roadmap Lays Out Superior CoWoS Packaging Systems, Ready For Up coming-Gen Chiplet Architectures & HBM3 Memory
TSMC has laid out its advanced packaging know-how roadmap and showcased its future-gen CoWoS options which are completely ready for future-gen chiplet architectures and memory remedies.
TSMC Lays Out Its Superior CoWoS Packaging Technological know-how Roadmap, 2023 Design and style All set For Chiplet & HBM3 Architectures
The Taiwanese-based mostly semiconductor large has attained rapid progress in deploying highly developed chip packaging technologies in the industry. Inside a 10 years, the organization has released five unique generations of CoWoS (Chip-on-Wafer-on-Substrate) offers that are at the moment deployed or currently being deployed in client and server house.
The organization expects to release its Gen 5 CoWoS packaging remedy later on this year which will push the transistor rely by 20x above the 3rd Gen packaging resolution. The new deal will occur with an interposer location enhance of 3 periods, 8 HBM2e stacks for up to 128 GB capacities, a model new TSV alternative, Thick CU interconnect, and a new TIM (Lid package deal). The most noteworthy answer that will make use of the Gen 5 packaging technologies from TSMC is specifically AMD’s MI200 ‘Aldebaran’ GPU.
The AMD Aldebaran GPU will be the first MCM GPU fabricated and made about at TSMC. The GPU will be powered by AMD’s CDNA 2 architecture and is envisioned to rock some insane specs these types of as more than 16,000 cores and 128 GB of HBM2E memory. NVIDIA’s Hopper GPU would also be making use of an MCM chiplet architecture and is envisioned to be manufactured at TSMC. This GPU is anticipated to launch in 2022 so we can assume NVIDIA to leverage from the Gen 5 alternative way too.
By Gen 6, TSMC will have a greater reticle space to combine additional chiplets and far more DRAM offers. The package layout has not nonetheless been finalized by TSMC expects to household up to 8 HBM3 DRAM and two compute chiplet dies on the similar bundle. TSMC is also going to give the latest SOC thermal answer in the variety of Metal Tim which is anticipated to lower the bundle thermal resistance to .15x more than Gel TIM applied in 1st Gen. This is even now far off and will be created for products and solutions that will be produced on the N3 process node so we are on the lookout at either CDNA 3 (MI300) or Ampere Following Next.